Vinay C Javali - Analog Layout Engineering Workspace

Hubballi, India

Vinay JavaliECE · 40nm

Vinay C Javali

Analog Layout Engineer

Electronics & Communication Engineer & Analog Layout Intern at YQ14 Technologies. Specializing in custom analog IC layout in 40nm CMOS nodes, Cadence Virtuoso, Calibre DRC/LVS, device matching, and 5G wireless network simulations. Graduate of KLE Technological University, Hubballi.

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About & Journey

From an electronics diploma to an Electronics and Communication degree at KLE Technological University, Hubballi, I’ve learned by building. With KLE TECH Motorsports, I helped secure SAE BAJA national ranks of 5th (2025) and 9th (2024).

Today, I’m an Analog Layout Intern at YQ14 Technologies, Bangalore, designing and verifying 40nm CMOS layouts with Cadence Virtuoso and Calibre.

Education

KLE Technological University

Bachelor of Engineering in Electronics and Communication

Hubballi, Karnataka. Comprehensive study in Semiconductor Devices, Analog Integrated Circuit Design, VLSI Design Flow, MOSFET Characteristics, Digital Signal Processing, Communication Systems, and 5G Networks. Active member of KLE TECH Motorsports (2023 – 2025).

Graduated

Tippu Shaheed Institute of Technology

Diploma in Electronics and Communication

Hubballi, Karnataka. Foundational coursework in Electronic Circuits, Linear Integrated Circuits, Digital Electronics, Microcontroller Systems, and Laboratory Circuit Testing.

Completed

Work Experience

Intern Analog Layout Engineer|YQ14 Technologies Pvt. Ltd.

Bangalore, India · Internship

Designing and implementing custom analog integrated circuit layouts in advanced 40nm CMOS technology using Cadence Virtuoso. Applying industry-standard physical design best practices including common-centroid matching, critical net shielding, differential signal routing, and guard-ringing for substrate noise isolation. Executing full DRC, LVS, and ERC verification decks using Siemens Calibre and Assura, minimizing parasitic resistance and capacitance to ensure post-layout timing and electrical integrity.

Cadence VirtuosoCalibre DRC/LVS40nm CMOSAssuraDevice MatchingParasitic MinimizationAnalog IC Layout

Jan 2026 — Present

Technical Skills & EDA Stack

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Cadence Virtuoso

Siemens Calibre

Cadence Assura

Cadence Spectre

LTspice

MATLAB

40nm CMOS Technology

Common-Centroid Matching

Floorplanning & Routing

DRC / LVS / ERC Verification

Parasitic Minimization

MOSFET Characteristics

5G NR Network Simulation

OpenAirInterface (OAI)

JNCIA-Junos

Embedded Systems

C Programming

C++

Python

Linux

Engineering Projects(6 Total · 6 Shown)

Analog IC & Layout

Voltage Regulator Layout Design in 40nm Technology

Designed and implemented the custom analog layout of an on-chip Voltage Regulator in 40nm CMOS technology using Cadence Virtuoso. Executed precision device matching, optimum floorplanning, differential routing, and guard ring isolation. Verified full design correctness through DRC and LVS checks using Calibre while optimizing silicon area, thermal dissipation, and loop stability.

Cadence Virtuoso40nm CMOSCalibre DRC/LVS+2

Hardware Design

Analog IC & Layout

CMOS Operational Amplifier Layout Design

Implemented a two-stage 40nm CMOS Operational Amplifier layout using Cadence Virtuoso. Applied industry-standard analog layout methodologies such as common-centroid and interdigitated transistor matching for differential input pairs, dummy poly gates, and parasitic minimization. Successfully passed all DRC, LVS, and ERC checks with zero design rule violations.

Cadence Virtuoso40nm CMOSCommon-Centroid Matching+2

Hardware Design

5G & Telecommunications

5G NR Network System-Level Simulation & Performance Evaluation

Developed a MATLAB-based 5G New Radio (NR) network simulator to evaluate multi-cell interference, Signal-to-Interference-plus-Noise Ratio (SINR), and throughput. Implemented 3GPP Urban Macrocell (UMa) channel propagation models to analyze spectral efficiency and beamforming performance under dense user deployment scenarios.

MATLAB5G NR3GPP UMa Model+2

Hardware Design

5G & Telecommunications

Testing & Deployment of 5G Private Network using OAI

Built and configured an end-to-end 5G Private Network testbed using OpenAirInterface (OAI). Verified gNodeB and 5G Core interconnectivity, performed throughput stress testing, and optimized radio link parameters, establishing zero-interruption high-reliability network transmission.

OpenAirInterface (OAI)5G Private NetworkSDR+2

Hardware Design

Machine Learning & Signal Processing

DeepFake Detection Study using Custom CNN

Developed an automated DeepFake image classification system using a custom Convolutional Neural Network (CNN). Implemented image preprocessing, facial alignment, and data augmentation in Python with TensorFlow and Keras, achieving 90.44% testing accuracy across benchmark datasets.

PythonTensorFlowKeras+2

Hardware Design

Analog IC & Layout

Analog Physical Verification & Sign-off Flow

Automated physical DRC/LVS verification run decks and parasitic extraction (PEX) for analog building blocks in 40nm CMOS. Integrated Cadence Virtuoso layout editor with Siemens Calibre to perform antenna rule checks, latch-up prevention, and critical net RC extraction.

Cadence VirtuosoCalibre PEXAntenna Rules+2

Hardware Design

Awards, Certifications & Leadership

SAE BAJA 2025 — All India Rank 5th (AIR 5)

AIR 5th

M-BAJA National Engineering Competition

Secured 5th Rank All India among 100+ collegiate engineering teams nationwide in the prestigious national off-road vehicle design and endurance challenge.

2025Verify

SAE BAJA 2024 — All India Rank 9th (AIR 9)

AIR 9th

M-BAJA National Engineering Competition

Achieved 9th Rank All India in the M-BAJA national vehicle engineering challenge, evaluating vehicle dynamics, electrical design, and endurance.

2024Verify

Juniper Networks — Junos Associate (JNCIA-Junos)

Certified

Juniper Networks Official Certification

Demonstrates fundamental networking knowledge, Junos OS routing and switching architecture, routing policy, and protocol operations.

CertifiedVerify

Full Stack Embedded Systems

Certified

Krutanic Training & Certification

Hands-on technical mastery in embedded systems architecture, C/C++ firmware development, microcontroller interfacing, and RTOS principles.

CertifiedVerify

KLE TECH Motorsports — Team Member

Leadership

KLE Technological University, Hubballi

Active team member contributing to vehicle design, electrical telemetry integration, system testing, and competitive track operations.

2023 – 2025Verify

Core Competencies & Soft Skills

Critical ThinkingAttention to DetailProblem SolvingTime ManagementAdaptabilityCommunication